This tutorial is about using the internal timers/counters of 8051. This will tackle the registers associated with the internal timers/counters of 8051 and this will also enumerate the steps on using the timers/counters of an 8051 microcontroller.
The Timers/Counters of AT89C2051
The AT89C2051 has two 16-bit Timer/Counters: Timer0 and Timer1. This means that it can time/count from 0 to 65535 (2^16-1). The timers can be used to generate accurate delays and the counters can be used to count events. An event can be anything. It can be a pulse, a push, a pull, or any stimulus.
Basic Registers of Timer/Counter
1. Timer0 Registers
Timer0 is a 16-bit timer/counter and it is accesed as TH0 (Timer0 high byte) and TL0 (Timer0 low byte).
2. Timer1 Registers
Timer1 is a 16-bit timer/counter and it is accesed as TH1 (Timer1 high byte) and TL1 (Timer1 low byte).
3. TMOD Register
The TMOD (timer mode) register sets the operational modes of Time0 and Timer1. It is 8 bits wide in which the upper nibble is for Timer1 and the lower nibble is for Timer0.
GATE: Gating control when set. Timer/Counter x is enabled only while INTx pin is high and TRx control pin is set. When cleared, Timer x is enabled whenever TRx control bit is set.
C/T: If C/T = 1, the counter operation is selected. If C/T=0, the timer operation is selected
M1: Mode bit 1
M0: Mode bit 0
When the timer operating mode is selected, the clock source of the timer is the same as the clock source of AT89C2051 (ex: external quartz crystal). The frequency of the timer’s clock source is equal to the frequency of At89C2051′s clock source divided by 12. If the clock source is a 12MHz quartz crystal, the timer’s clock frequency is equal to 12MHz/12 = 1MHz.
4. TCON Register
The TCON (Timer/counter control) register is responsible to the control and status bits of AT89C2051′s timers/counters (and external interrupts).
| TF1 | Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine. |
| TR1 | Timer 1 run control bit. Set/cleared by software to turn Timer/Counter on/off. |
| TF0 | Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine. |
| TR0 | Timer 0 run control bit. Set/cleared by software to turn Timer/Counter on/off. |
| IE1 | Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. |
| IT1 | Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. |
| IE0 | Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. |
| IT0 | Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. |
THIS IS AN EXCELLENT JOB. AS EXPLICIT AS IT CAN BE!